1. Field of Invention
The present invention relates to fabrication of via in semiconductor device. More particularly, the present invention relates to a method of fabricating an unlanded via.
2. Description of Related Art
As the size of the semiconductor device is gradually reduced, the chances of misalignment during photolithography are increased. When misalignment occurs during via formation, the dielectric layer adjacent to the metal layer is easily overetched.
Referring to FIG. 1A, patterned metal layers 102a, 102b are formed on a substrate 100. As shown in FIG. 1B, an inter-metal dielectric layer (IMD) 104 is formed over the substrate 100 to cover the metal layers 102a, 102b. The IMD layer 104 has an uneven topography due to the metal layers 102a, 102b. Thereafter, chemical mechanical polishing (CMP) is performed to planarize the IMD layer 104.
The metal layers 102a, 102b with small area and large area, respectively, are simultaneously formed on a single wafer. The metal layers 102a, 102b usually belong to dense pattern and less dense pattern, respectively. Accordingly, when CMP in the forgoing process is carried out, a thickness difference `h` of the IMD layer 104 over the metal layer 102a, 102b is created due to the polishing characteristic of CMP, as illustrated in FIG. 1C. As a result, the difference `h` of the IMD layer 104 thickness is about 2000 angstroms.
The IMD layer 104 is then patterned and unlanded via openings 106a, 106b are respectively formed on the metal layer 102a, 102b, as shown in FIG. 1D. In order to completely expose the metal layer 102b so as to create a good contact between the metal and the via, the IMD layer 104 with a thicker thickness has to be over-etched when forming the via opening 106b. As a result, this over-etching process causes serious over-etching of the IMD layer 104 on and adjacent to the metal layer 102a when forming an unlanded via opening 106a within the thinner IMD layer 104. The most serious problem is the IMD layer 104 being over-etched to expose the sidewall 108 of the metal layer 102a and the substrate 100 underlying the IMD layer 104. When metal material is deposited in the unlanded via openings 106a, 106b to form vias, the over-etching of the IMD layer 104 on the metal 102a induces problems such as an increase of RC resistance.